Counter architecture for online DVFS profitability estimation
US8812808B2 · kind B2 · utility
6Cited by
1References
13Claims
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Key dates
| Filing date | Dec 10, 2010 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Aug 1, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counter architecture and a corresponding method are provided for estimating a profitability value of DVFS for a unit of work running on a computing device. The counter architecture and the corresponding method are arranged for dividing total execution time for executing a unit of work on the computing device into a pipelined fraction subject to clock frequency and a non-pipelined fraction due to off-chip memory accesses, and for estimating the DVFS profitability value from the pipelined and the non-pipelined fraction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.