Patent · US Active

Structural feature formation within an integrated circuit

US8812997B2 · kind B2 · utility

0Cited by
4References
12Claims
0Family size

Assignee

Inventor

Key dates

Filing dateMay 18, 2011
Grant dateAug 19, 2014
Priority date—
Expiry dateMar 7, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An integrated circuit is formed using an lithographic process including a stage of forming a lithographic layer from a plurality of separately printed pattern layers. Within the integrated circuit there is formed a circuit including at least two devices that are matched devices such that the performance of the circuit is degraded if the match devices deviate from having matched performance characteristics. Dummy contacts 32 (structural features) are provided within the circuit design so as to force allocation of functional contacts (structural features) of the matched devices into the same pattern layer thereby reducing inter-device variation in contact position and/or size.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.