System and method for efficient and optimal minimum area retiming
US8813001B2 · kind B2 · utility
5Cited by
15References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2009 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Feb 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for use in electronic design software efficiently and optimally produces minimized or reduced register flip flop area or number of registers/flip flops in a VLSI circuit design without changing circuit timing or functionality. The method dynamically generates constraints; maintains the generated constraints as a regular tree; and incrementally relocates registers/flip flops and/or the number of registers/flip flops in the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.