Reassembly-free deep packet inspection on multi-core hardware
US8813221B1 · kind B1 · utility
15Cited by
12References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2008 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Jul 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/1408
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some embodiments of reassembly-free deep packet inspection (DPI) on multi-core hardware have been presented. In one embodiment, a set of packets of one or more files is received at a networked device from one or more connections. Each packet is scanned using one of a set of processing cores in the networked device without buffering the one or more files in the networked device. Furthermore, the set of processing cores may scan the packets substantially concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.