Patent · US Active

TFT array substrate and manufacturing method thereof

US8816346B2 · kind B2 · utility

2Cited by
31References
6Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 31, 2012
Grant dateAug 26, 2014
Priority date
Expiry dateOct 31, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/60

Abstract

A TFT array substrate and a manufacturing method thereof, where the TFT array substrate includes a substrate; a gate line and a gate electrode integrated therewith, which are covered by a gate insulating layer, a semiconductor layer, and a ohmic contact layer sequentially. An insulating layer is formed on the resulting substrate and on both sides of the gate line and the gate electrode, the gate insulating layer, the semiconductor layer, and the ohmic contact layer. A trench is then formed in the ohmic contact layer to divide the ohmic contact layer over the semiconductor layer. A data line and first and second source/drain electrodes are then formed on the insulating layer and the ohmic contact layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.