Cascaded class D amplifier with improved linearity
US8816764B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Oct 9, 2013 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Oct 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/2173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier includes a first stage, a second stage coupled to the first stage, and a summation circuit. The first stage is configured to receive an analog input signal, convert the analog input signal to a digital signal, and output an intermediate analog output signal in response to the digital signal. The second stage is configured to output a second analog intermediate output signal based on a scaled pulse width modulation quantization error of the first stage. The summation circuit is configured to combine the first and second analog intermediate output signals to generate an amplified output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.