Data interface alignment
US8816885B2 · kind B2 · utility
0Cited by
5References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Jun 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4902
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus may include a de-serializer to convert serial data into two parallel data streams, and a control unit to provide a first update signal and a second update signal based on a bit count of the serial data. The apparatus may further include a target component having an input bus, the input bus including a first portion and a second portion. The apparatus may further include a first output unit to provide the first set of parallel data to the first portion of the input bus, and a second output unit to provide the second set of parallel data to the second portion of the input bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.