Segmented column-parallel analog-to-digital converter
US8816892B2 · kind B2 · utility
5Cited by
4References
16Claims
0Family size
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Key dates
| Filing date | Oct 20, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Oct 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation A/D converter which includes a sub ranging classifier that receives an input signal and classifies said input signal according to plural different highest resolution bits, to determine a range of the input signal, and creating a set of most significant bits based on said range, said subranging classifier also setting and determining an offset based on said range, and a successive approximation A/D converted that converting lowest resolution parts of the input signal as adjusted by the offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.