Semiconductor memory device
US8817551B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Apr 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array block including a plurality of memory cells each including a data holding circuit configured to store data using a first and a second circuit elements and a transistor configured to connect the data holding circuit and a bit line together, sense amplifiers connected to bit lines directly or via switches, and a dummy memory cell array including a plurality of dummy memory cells each having the same circuit configuration as that of the memory cell with respect to the element size and the layout configuration. The plurality of dummy memory cells each include at least one inverter circuit configuration, and are connected together by the inverter circuits being connected together in series. An output signal of the inverter circuit of one in the final stage of the dummy memory cells is an activation signal for the sense amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.