Dual rail memory
US8817568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Oct 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first voltage circuit coupled to internal first nodes of memory cells in the one of the plurality of columns and a second voltage circuit coupled to internal second nodes of the memory cells in the one of the plurality of columns. The first voltage circuit is configured to provide one of a first supply voltage and a second supply voltage lower than the first supply voltage to the internal first nodes. The second voltage circuit is configured to provide one of a first reference voltage and a second reference voltage higher than the first reference voltage to the internal second nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.