System and method for performing timing control
US8817937B2 · kind B2 · utility
2Cited by
1References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Nov 21, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing control apparatus includes an adder and a comparator. The adder adds unused time error in each of a plurality of periods to form a cumulative value, and the comparator compares the cumulative value to a reference value. The unused time error is computed during operation of a first clock, and a control signal is generated to switch from the first clock to a second clock based on an output of the comparator. The frequency of the first clock is greater than a frequency of the second clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.