Offset cancellation for DC isolated nodes
US8818271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2013 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Dec 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B5/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.