Feedback programmable data strobe enable architecture for DDR memory applications
US8819354B2 · kind B2 · utility
5Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2005 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Feb 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.