Method and system for clock edge synchronization of multiple clock distribution integrated circuits by configuring master device to produce at least one gated clock output signal
US8819472B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2011 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Mar 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for clock edge synchronization among a plurality of devices. One of the plurality of devices is designated as a master device and one or more remaining devices as slave devices. The master device is configured for providing one or more gated master output clock signals based on a synchronization input signal and an input clock signal. The master device may be further configured to generate one or more gated master clock outputs to drive one or more slave devices, or to provide one or more slave synchronous master clock outputs. The one or more slave devices are configured for producing one or more slave output clock signals, based on the synchronization input signal and corresponding one or more gated master output clock signals. The one or more slave output clock signals are clock edge synchronized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.