Electronic circuit design method
US8819615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2013 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Sep 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.