High linearity bandgap engineered transistor
US8823011B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2011 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Oct 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6713
Abstract
A high linearity bandgap engineered transistor device is provided. In one example configuration, the device generally includes a substrate and an oxide layer formed on the substrate. The device further includes a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap of 1.35 eV or higher and is lattice matched to the substrate. The device further includes a source-drain material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain material contacts the wide-bandgap body material. The wide-bandgap body material is also lattice matched to the source-drain material. The device further includes a gate material formed over the gate dielectric layer. Other features and variations will be apparent in light of this disclosure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.