Data transition density normalization for half rate CDRs with bang-bang phase detectors
US8823429B1 · kind B1 · utility
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3References
21Claims
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Key dates
| Filing date | Nov 19, 2013 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Nov 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0896
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery circuit includes a phase detector circuit, a charge pump circuit, and a voltage controlled oscillator. The phase detector circuit receives a data signal from an external device and a clock signal from the voltage controlled oscillator and generates a first and a second phase difference signal. The charge pump circuit includes an OR gate receiving on its inputs the first and the second phase difference signals and configured to generate a current if the first and/or second phase difference signal is high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.