Low power data recovery
US8823432B2 · kind B2 · utility
4Cited by
15References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4902
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.