In-system reconfigurable circuit for mapping data words of different lengths
US8823561B1 · kind B1 · utility
5Cited by
3References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 20, 2012 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Apr 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W88/085
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A de-mapping circuit for de-mapping input words of a first length into output words of a second length different from the first length. In one embodiment, the circuit includes a word register of the first length and temporary registers of the second length. The word register successively stores each of the inputs words in response to cycles of a clock. The temporary registers temporarily store the output words. Multiplexers configured by address signals select bits from stored input words and store the selected bits into the temporary registers to form temporarily stored output words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.