Anti-aliasing sampling circuits and analog-to-digital converter
US8823572B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2012 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Dec 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sampling circuit, such as the sampling circuit of a successive approximation analog-to-digital converter (ADC), provides anti-aliasing filtering of a sampled input signal. The circuit samples the input signal using multiple capacitors, wherein each capacitor samples the input signal at a distinct time during a sampling time interval. The circuit combines the samples stored on different capacitors during a conversion time interval, and generates a digital output signal using the combined samples. In one example, a first bit of the output signal is generated using a sample stored on a first capacitor, and second bit of the output signal is generated using a sample stored on a second capacitor. In another example, the circuitry performs finite or infinite impulse response (FIR or IIR) filtering of the input signal, where a filter characteristic is determined by the relative sizes of the capacitors used for sampling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.