Static RAM
US8824197B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2012 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Dec 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static RAM includes: a plurality of word lines; a plurality of pairs of local bit lines; a plurality of memory cells arranged in correspondence with intersections of the plurality of pairs of local bit lines and the plurality of word lines; a capacitance shared circuit arranged for each of the plurality of pairs of local bit lines; a common connection line connecting the plurality of capacitance shared circuits; and a pair of global bit lines connected to the plurality of pairs of local bit lines, wherein the capacitance shared circuit includes two N-channel transistors connected between the pair of local bit lines and the common connection line corresponding to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.