Data storage circuit that retains state during precharge
US8824215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2012 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Aug 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.