Patent · US Active

Method and apparatus of reducing leakage power in multiple port SRAM memory cell

US8824230B2 · kind B2 · utility

3Cited by

6References

58Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Michael ThaiThanh Phan · Cary, US
Manish Garg · Cary, US
David Paul Hoff · Raleigh, US

Key dates

Filing date	Sep 30, 2011
Grant date	Sep 2, 2014
Priority date	—
Expiry date	Feb 22, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C5/148
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.