Matrix decomposition using dataflow techniques
US8825730B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2011 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Jan 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficient and scalable circuitry for performing Cholesky decomposition is based on a dataflow style architecture which uses self-timed circuitry and eliminates the need for complicated state machines. Calculations are ordered such that partial sums of products are created in parallel subject to data dependency requirements, allowing a single accumulator to perform the summation. A Vector FIFO receives a partial sum of products from a vector processing engine. A Feedback FIFO stores partial results and feeds the partial results back to the data path based on signals from a dataflow controller. The circuitry is flexible to allow different matrix sizes, speed grades, and target frequencies without recompilation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.