Method and system for real-time error mitigation
US8826072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2012 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Oct 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1471
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of organizing on-chip data memory in an embedded system-on-chip platform whereon a deterministic application needs to meet a guaranteed constraint on its functional system behavior is disclosed. In one aspect, the method includes: a) dividing the deterministic application into blocks one of which corresponds to a part of a subtask of the application, the block receiving input data and/or generating output data and including internal intermediate data for transforming the input data into the output data, b) splitting the internal intermediate data into state and non-state data, and c) putting the non-state data and a part of the state data in a protected buffering module being part of the data memory and being provided with an error detection and correction module, so that they are available for mitigating the effect of faults on the functional system behavior on-line while meeting the at least one guaranteed constraint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.