Automating current-aware integrated circuit and package design and optimization
US8826203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2013 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | May 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.