Method of generating technology file for integrated circuit design tools
US8826207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2007 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | May 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.