Integrated semiconductor device and fabrication method
US8828814B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Feb 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for fabricating an integrated semiconductor device. The method includes providing a semiconductor substrate having a first active region, a second active region and a plurality of isolation regions; forming a first gate dielectric layer on one surface of the semiconductor substrate; and forming a plurality of substituted gate electrodes, a layer of interlayer dielectric and sources/drains. The method also includes forming a first trench and a second trench; and covering the first gate dielectric layer on the bottom of the first trench. Further, the method includes removing the first dielectric layer on the bottom of the second trench; subsequently forming a second gate dielectric layer on the bottom of the second trench; and forming metal gates by filling the first trench and second trench using a high-K dielectric layer, followed by completely filling the first trench and the second trench using a gate metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.