Reducing variation by using combination epitaxy growth
US8828850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Dec 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.