Process for preparing a bonding type semiconductor substrate
US8829488B2 · kind B2 · utility
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50References
7Claims
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Key dates
| Filing date | Aug 27, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Sep 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a laminate containing a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×1018 cm3 or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.