Semiconductor memory device having three-dimensionally arranged memory cells, and manufacturing method thereof
US8829593B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2010 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | May 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.