Current reuse frequency divider and method thereof and voltage control oscillator module and phase-locked loop using the same
US8829966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current reuse frequency divider including a first latch circuit and a second latch circuit is provided. The first latch circuit includes a first transistor pair and a second transistor pair. The first latch circuit receives a first differential oscillation signal through bodies of the first transistor pair and the second transistor pair and divides the frequency of the first differential oscillation signal to generate a second differential oscillation signal. The second latch circuit is coupled to the first latch circuit and includes a third transistor pair and a fourth transistor pair. The second latch circuit receives the first differential oscillation signal through bodies of the third transistor pair and the fourth transistor pair and divides the frequency of the first differential oscillation signal to generate a third differential oscillation signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.