Methods and circuits for operating a parallel DMOS switch
US8829975B2 · kind B2 · utility
4Cited by
14References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Nov 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0054
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and corresponding circuits for operating a parallel DMOS switch that includes a pair of P-type DMOS devices connected in series with each other and in parallel with a pair of N-type DMOS devices connected in series with each other. The method and circuits involve turning the switch on by applying gate signals to the DMOS device pairs which are generated using at least one source voltage of a DMOS device pair. The switch is turned off by setting the gate signals equal to the respective source voltages of the DMOS device pairs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.