System incorporating power supply rejection circuitry and related method
US8829982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Jul 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method providing power supply rejection. One embodiment provides for power supply rejection in PLL or DLL circuitry. First subcircuitry provides second subcircuitry a supply voltage which is a filtered version of power from an external source. The first subcircuitry includes a first field effect transistor and a first low pass filter coupled to receive a signal from the external power source during operation of the second subcircuitry. The filter is coupled to provide a filtered version of the power source signal to the gate of the first transistor, so that when a first source/drain region of the first transistor is connected to receive power from the external source and the gate of the first transistor receives the filtered version of the power source signal, the second source/drain region of the first transistor provides a first modified version of the power received from the external source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.