ESD protection against charge coupling
US8830639B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Jan 12, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Dec 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
This document discusses among other things apparatus and methods for reducing ESD damage to buffer circuits. In an example, an output buffer can include an output, a first transistor configured to couple the output to a high logic supply rail, a second transistor configured to couple the output node to a low logic supply rail, pre-driver logic configured to drive a gate of the first transistor and a gate of the second transistor, and a first resistor configured to reduce electrostatic discharge (ESD) induced current between the first transistor and the pre-driver logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.