Semiconductor storage device
US8830740B2 · kind B2 · utility
10Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Sep 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/75
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.