Semiconductor storage device
US8830760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2013 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Feb 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes memory cells and a sense amplifier including a sense node that transmits a voltage according to a current flowing in one of the memory cells and detects logic of data based on the voltage of the sense node. A write sequence of writing data in a selected cell is performed by repeating write loops each including a write stage of writing data in the selected cell and a verify read stage of verifying that the data has been written in the selected cell by performing discharge from the sense node through the selected cell. The sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop, a period of discharge from the sense node to the selected cell at the verify read stage in a second write loop following the first write loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.