Memory circuits having a plurality of keepers
US8830782B2 · kind B2 · utility
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3References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Mar 5, 2013 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Mar 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit including a memory circuit, the memory circuit includes a first plurality of memory arrays and a first plurality of keepers, each keeper of the first plurality of keepers is electrically coupled with a corresponding one of the first plurality of memory arrays. The memory circuit further includes a first current limiter electrically coupled with and shared by the first plurality of keepers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.