Virtualizing processor memory protection with “L1 iterate and L2 drop/repopulate”
US8832351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2010 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Dec 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computing system including a processor and virtualization software including a guest operating system (OS) that utilizes a guest domain access control register (DACR) containing domain access information and guest page tables including first level page tables (L1 page tables) and second level page tables (L2 page tables), which guest page tables contain: (a) domain identifiers used to obtain domain access information from the guest DACR and (b) access permission information, wherein the domain access information and the access permission information are combined to provide an effective guest access permission, in accordance with one embodiment, a method for providing shadow page tables and processor DACR settings that virtualize processor memory protection includes: the virtualization software providing a shadow page table wherein: (a) domain identifiers in the shadow page table are used to identify domain access information in the processor DACR that are mapped from the domain access information in the guest DACR; and (b) access permissions in the shadow page table that are mapped from the effective access permission information in the guest page tables and guest DACR; wherei…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.