Scalable processing unit
US8832412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Jun 29, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Various methods and systems are provided for processing units that may be scaled. In one embodiment, a processing unit includes a plurality of scalar processing units and a vector processing unit in communication with each of the plurality of scalar processing units. The vector processing unit is configured to coordinate execution of instructions received from the plurality of scalar processing units. In another embodiment, a scalar instruction packet including a pre-fix instruction and a vector instruction packet including a vector instruction is obtained. Execution of the vector instruction may be modified by the pre-fix instruction in a processing unit including a vector processing unit. In another embodiment, a scalar instruction packet including a plurality of partitions is obtained. The location of the partitions is determined based upon a partition indicator included in the scalar instruction packet and a scalar instruction included in a partition is executed by a processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.