LDPC decoder architecture
US8832534B1 · kind B1 · utility
2Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Dec 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1111
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, devices, and methods are disclosed for a novel LDPC decoder. An architecture is described to implement a novel sequence of bit node processing (BNP) and check node processing (CNP) operations. More specifically, the BNP may be split into two parts: a BNP accumulator and a BNP extrinsic information calculator. This separation of processing modules may provide for fewer read and write operations to and from edge memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.