Storage devices with secure debugging capability and methods of operating the same
US8832843B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 20, 2010 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Jan 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.