Mixed mode multiple switch integration of multiple compound semiconductor FET devices
US8835239B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2014 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Jan 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
Various aspects of the technology include a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.