Programmable logic switch

US8836007B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Mari Matsumoto · Yokohama, JP
• Shinichi Yasuda · Tokyo, JP
• Masato Oda · Yokohama, JP
• Kosuke Tatsumura · Yokohama, JP
• Koichiro Zaitsu · Yokohama, JP
• Shuou Nomura · Kawasaki, JP
• Yoshihisa Iwata · Yokohama, JP

Key dates

• Filing date: Feb 21, 2013
• Grant date: Sep 16, 2014
• Expiry date: Feb 21, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00

Abstract

According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line.