Power factor correction circuit of an electronic ballast
US8836230B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2010 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Mar 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B41/28
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
This invention relates to a power factor correction circuit of an electronic ballast. The electronic ballast includes a rectification circuit, a first capacitive element and an inverter. The power factor correction circuit comprises a unidirectional element, an inductive element and a second capacitive element. The unidirectional element is connected in series with the inductive element, and the second capacitive element is connected in parallel with the unidirectional element and the inductive element. A junction of the unidirectional element and the second capacitive element is coupled to a first output terminal of the rectification circuit, a junction of the inductive element and the second capacitive element is coupled to an input terminal of the inverter, and the first capacitive element is coupled between a second output terminal of the rectification circuit and a junction of the unidirectional element and the inductive element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.