Minimizing power consumption in asynchronous dataflow architectures
US8836372B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2013 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Mar 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.