Systems and methods for reducing power supply noise or jitter
US8836384B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2013 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Aug 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00346
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. In one example, a power distribution network may supply power to components of an integrated circuit and data driver circuitry may draw first current to drive a data signal. Compensation circuitry may draw second current at times when the data driver circuitry is not drawing the first current, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device (e.g., the power distribution network).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.