Smart card clock generator circuits wth autonomous operation capability and method of operating the same
US8836388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a reference clock signal generator circuit configured to generate a reference clock signal in response to a carrier signal and a clock selection signal generator circuit configured to generate a clock selection signal in response to the carrier signal. The apparatus further includes a multiplexer (MUX) circuit configured to selectively output the reference clock signal and a PLL output clock signal in response to the clock selection signal and a phase-locked loop (PLL) circuit configured to receive the selectively output signal between the reference clock signal and the PLL output clock signal at a reference input thereof and to generate the PLL output clock signal therefrom. An ISO 14443 type A smart card may include such apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.