Use of logic circuit embedded into comparator for foreground offset cancellation
US8836549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2011 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Feb 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.