Guarded electrical overstress protection circuit
US8837099B2 · kind B2 · utility
4Cited by
7References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2009 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Dec 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.